1. Field of the Invention
The present invention relates to a method of forming a conductive layer and, more particularly, to a selective deposition process using a plasma.
2. Description of the Related Art
In resent years, along development of a highly integrated, high-speed, high-density circuit such as ultra LSIs (large scaled integrated circuit), in order to form a gate electrode and to deposit a conductive material into a contact hole or a through hole, a technique for selectively depositing a refractory metal such as W (tungsten) having a low resistance 1/10 or less that of polycrystalline silicon has received a great deal of attention.
As a means for forming a thin metal film by selective deposition, a CVD (chemical vapor deposition) apparatus is available. In the CVD apparatus, a substrate is rapidly heated with infrared rays in order to maintain its selectivity, and a film is grown on the surface of the substrate by a film forming gas.
In formation of a thin metal film by using the CVD apparatus, when a substrate to be treated such as a silicon wafer is transferred from a previous step to the CVD apparatus, a natural oxide (SiO.sub.2) film having a thickness of, e.g., several tens of .ANG. is formed on the surface of a silicon wafer. When a thin metal film is formed on the silicon wafer on which the natural oxide film is formed, a contact resistance between the silicon wafer and the thin metal film is increased, and the thin metal film is peeled from the silicon wafer, thus degrading the quality of the semiconductor device.
In order to prevent this and improve the quality of the semiconductor device, the natural oxide film on the surface of the silicon wafer is removed by dry etching, and then a CVD process may be performed.
When this dry etching and CVD process are performed in the same chamber, the following problem is posed.
A plasma generating electrode for etching must be arranged in the CVD apparatus. However, a heavy metal such as Fe may be released from the plasma generating electrode during etching. This heavy metal contaminates a gate electrode or a diffusion region and causes degradation of device performance.
During etching, the silicon wafer may be damaged by plasma ion bombardment on the surface of the silicon wafer. In order to prevent this, the silicon wafer must be protected against the plasma. For this purpose, the structure of the chamber must be modified.
Conventional techniques concerning the modifications of the structure of the chamber are described in Published Unexamined Japanese Patent Application Nos. 60-221572, 60-238134, 61-95887, 61-231166, 62-213112, 62-250652 and the like. These prior art applications disclose a combination of a vacuum chamber and another chamber. However, no description is made about removal the natural oxide by dry etching from the surface of a silicon wafer and performance of a subsequent CVD process.